The present application relates generally a design structure, and more specifically to a design structure for saving cache array power through valid bit detection.
Random access memory (RAM) most commonly refers to computer chips that temporarily store dynamic data to enhance computer performance. By storing frequently used or active files in random access memory, a computer may access the data faster than if the computer retrieves the data from a far-larger hard drive. Random access memory is volatile memory, meaning it loses its contents once power is cut. This is different from non-volatile memory such as hard disks and flash memory, which do not require a power source to retain data. When a computer shuts down properly, data located in random access memory is committed to permanent storage on the hard drive or flash drive. At the next boot-up, RAM begins to fill with programs automatically loaded at startup and with files opened by the user.
Random access memory, which may also be referred to as cache memory arrays, is comprised of a plurality of memory cells having an individual logic circuit associated with each memory cell. Cache memory arrays may also employ the concept of a valid bit. Each logical row of memory cells contains at least one bit used to indicate whether the data stored is valid or invalid. Traditionally, the lookup would occur regardless of the state of the valid bit. Additional logic after the memory array output would discard the data returned from a read operation if the value stored for the valid bit denoted invalid data. The memory cell used to store data in an invalid bit may be different than traditional cells, such as the 6T cell. This difference consists of a reset port that may switch the state of the cell without the need for a standard wordline driver enabled access.